Details
| System Name | PARAM Trinetra |
| Site Name | Centre for Development of Advanced Computing (C-DAC) |
| City | Pune |
| State | MAHARASHTRA |
| Vendor | OEM:Supermicro, Bidder:Netweb Technologies |
| Installation Date | 01-JAN-2022 |
SYSTEM |
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| Description | The Trinetra test cluster consists of 12compute nodes having peak computing capacity of 10.6 TFlops. Each node has Intel Xeon Skylake processors (Gold 5118, 24C, 2.3 GHz) and 96 GB memory. The cluster is build using C-DAC’s indigenously developed Trinetra interconnect. Trinetra is 3D-Torus based interconnect. This system is designed and implemented by the HPC Technologies Group, C-DAC under National Supercomputing Mission (NSM). |
| Processor Socket | 2 |
| Node | 12 |
BENCHMARK |
|
| MPI | MVAPICH2 |
| Rpeak | 10.59 TFlops |
| Rmax | 7.87 TFlops |
Power Consumption |
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| Power | 1200 kW |
Software |
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| Operating System | CentOS 7 |